| 摘要 |
A partial linearly tagged cache memory system includes a cache storage coupled to a linear tag logic unit. The cache storage may store a plurality of cache lines. The cache storage may also store a respective partial linear tag corresponding to each of the plurality of cache lines. The linear tag logic unit may receive a cache request including a linear address. If a subset of bits of the linear address match the partial linear tag corresponding to a particular cache line, the linear tag logic unit may select that particular cache line. The linear address includes a first subset of bits forming an index and a second subset of bits. The partial linear tag corresponding to the particular cache line includes some, but not all, of the second subset of bits.
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