发明名称 LAYOUT STRUCTURE OF MULTIPLEXER CELL
摘要 PROBLEM TO BE SOLVED: To provide a layout structure of a multiplexer cell in which structure wiring trucks of a METAL2 layer upon one chip being laid out, which trucks are possessed by a four input multiplexer inverter, are increased. SOLUTION: The layout structure of a multiplexer cell has a layout structure of a primitive cell obtained by arranging cell lines, each cell line consisting of P channel transistors and N channel transistors, into upper and lower two lines, and a plurality of transistors constructing a transfer gate are disposed on the upper side of the cell lines and on the lower side of the same. Further, output terminals of the plurality of the transistors disposed as above are connected vertically through a METAL2 wiring while permitting the METAL2 wiring astride the upper and lower cell lines. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004260064(A) 申请公布日期 2004.09.16
申请号 JP20030050968 申请日期 2003.02.27
申请人 NEC ELECTRONICS CORP 发明人 HIDAKA ITSUO
分类号 H01L21/822;H01L21/82;H01L27/02;H01L27/04;H01L27/10;H01L27/118;H01L29/73;H03K17/687;H03K17/693;(IPC1-7):H01L21/82 主分类号 H01L21/822
代理机构 代理人
主权项
地址