发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 <p>A PLL circuit comprising a loop filter with at least a first and a second bandwith is provided. The first bandwith of the loop filter is determined by a first network of circuit components and used out of the linear rangs of the PLL circuit and the second bandwith is determined by a second network of circuit components and used within the linear range of the PLL circuit. A node of said second network is charged to a voltage level given by a node of said first network while the second network is switched off. When the second network is switched in, no long lasting charging process is required. Therefore, the lock time of the PLL circuit is reduced.</p>
申请公布号 WO2004079914(A1) 申请公布日期 2004.09.16
申请号 WO2003EP02371 申请日期 2003.03.07
申请人 FUJITSU LIMITED;MARTON, WALTER 发明人 MARTON, WALTER
分类号 H03H1/02;H03L7/089;H03L7/093;H03L7/107;H03L7/18;(IPC1-7):H03L7/107 主分类号 H03H1/02
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