发明名称 Self aligned channel implant, elevated S/D process by gate electrode damascene
摘要 A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.
申请公布号 US6790756(B2) 申请公布日期 2004.09.14
申请号 US20030385954 申请日期 2003.03.11
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY 发明人 HU CHU-WEI;WENG JIUE-WEN;LIN CHUNG-TE;KUO SO WEIN
分类号 H01L21/265;H01L21/336;H01L29/10;H01L29/78;(IPC1-7):H01L21/320 主分类号 H01L21/265
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