发明名称 |
Hard macro having an antenna rule violation free input/output ports |
摘要 |
Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a port level metallic conductor of an I/O port positioned at a low level metalization layer and an electrical connection between the port level metallic conductor and a gate conductor of the I/O transistor. The electrical connection includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.
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申请公布号 |
US6792578(B1) |
申请公布日期 |
2004.09.14 |
申请号 |
US20010878499 |
申请日期 |
2001.06.11 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
BROWN JEFFREY S.;CHAFIN CRAIG R. |
分类号 |
H01L23/485;(IPC1-7):G06F17/50;G01R31/26;H01L23/62 |
主分类号 |
H01L23/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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