发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the dimensional controlability of a resist pattern for trench formation. SOLUTION: A via hole 3 connecting a Cu wiring 1 is formed in an interlayer insulation film 2 covering the Cu wiring 1. A conductive polymer 4 is buried in the via hole 3 through electrolysis. A resist pattern 5 is formed on the interlayer insulation film 2 by photoengraving, and a substrate is etched while the resist pattern 5 is used as a mask, so as to form a trench 6 connected with the via hole 3. Then, the resist pattern 5 and the conductive polymer 4 are removed. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004253659(A) 申请公布日期 2004.09.09
申请号 JP20030043303 申请日期 2003.02.20
申请人 RENESAS TECHNOLOGY CORP 发明人 SAITO TAKAYUKI
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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