发明名称 Low power long code synchronization scheme for sleep mode operation of CDMA systems
摘要 In one embodiment, the present invention is a method for conserving power supplied to a linear feedback shift register (LFSR) long code (LC) generator, the method including steps of operating the LC generator during pre-assigned time slots; shutting off the LC generator during standby periods between the pre-assigned time slots; and priming starting states of the LC generator for synchronization with pre-assigned time slots following a standby period. This embodiment of the present invention enables power to be removed from the LFSR LC generator as well as the LFSR clock. Because the accuracy of the LFSR clock is usually derived from a system master transistor-controlled crystal oscillator (TCXO), and because the LFSR clock operates at a relatively high rate, the TCXO can also be powered down to conserve power. A low frequency, low power clock source can then be used instead of the higher powered clock source and TCXO to maintain operation of the mobile during the mobile sleep state.
申请公布号 US6788668(B1) 申请公布日期 2004.09.07
申请号 US20000515222 申请日期 2000.02.29
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 SHAH YOGENDRA CHAMPAKLAL;AGHAZADEH-ALAVI REZA;TOUSSI KARIM NASSIRI;SAMBHWANI SHARAD D.
分类号 H04B7/26;(IPC1-7):H04B7/216 主分类号 H04B7/26
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