发明名称 |
ELECTRON BEAM LITHOGRAPHY SYSTEM, METHOD FOR EXPOSING HOLE PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE TO SHORTEN INTERVAL OF EXPOSURE TIME |
摘要 |
<p>PURPOSE: An electron beam lithography system is provided to shorten an interval of exposure time by decreasing the number of shots in performing an exposure process on a hole pattern of a logic device. CONSTITUTION: An electron beam lithography system performs a partial exposure at a time by using electron beam, including the second molding aperture(102) with a cell(21) in which a plurality of hole patterns of a logic device is installed. In the cell, a plurality of hole patterns are disposed at an interval that is natural number times the interval of power lines in the logic device.</p> |
申请公布号 |
KR20040076210(A) |
申请公布日期 |
2004.08.31 |
申请号 |
KR20040011740 |
申请日期 |
2004.02.23 |
申请人 |
SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC. |
发明人 |
TOMO YOICHI |
分类号 |
G03F7/20;H01L21/027;(IPC1-7):H01L21/027 |
主分类号 |
G03F7/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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