A protection for ICs against ESD transients includes a circuit with a master circuit driving a slave circuit. The master circuit responds to ESD voltage V(t). The slave circuit comprises parallel shunt devices having common inputs. The output of the master circuit is coupled to the common inputs. As V(t) increases the master circuit applies a portion of V(t) to the input of the slave circuit shunt devices. The threshold voltage Vt1 at which the slave circuit shunt devices would otherwise turn on to a lower value Vt1' closer to the holding voltage Vh of the shunt devices. All of the slave circuit devices turn on substantially simultaneously at about Vt1' close to Vh, thereby shunting the ESD transient to ground at a lower value of V(t). The master and slave circuits are inactive during normal IC operation.
