发明名称 |
METHOD AND STRUCTURE FOR FABRICATING VERTICAL TRANSISTOR CELL AND TRANSISTOR CONTROL MEMORY CELL TO AVOID ACCUMULATION OF CHARGE CARRIERS AND FLOATING BODY PHENOMENON |
摘要 |
PURPOSE: A method for fabricating a vertical transistor cell is provided to prevent accumulation of charge carriers in an active region and a floating body phenomenon without increasing an area required by a transistor cell by making the active region adjacent to a transistor cell become a part of a main body of an adjacent layer and by connecting the active region and the main body of the adjacent layer with each other. CONSTITUTION: Vertical transistor cells(81) are disposed in a transistor cell array formed in a substrate, made of columns in the X-axis direction and rows in the Y-axis direction. A source/drain region(2) under the transistor cell is coupled to a common connection plate. A source/drain region(4) above the transistor cell comes in contact with a storage capacitor of a DRAM(dynamic random access memory) memory cell. An active trench(5) located between the transistor cells with wordlines(521) is formed along the X-axis direction. A gate electrode is partially formed by the wordlines. A conductive channel in the active region located between upper and lower source/drain junction regions is controlled by a voltage applied to the gate electrode.
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申请公布号 |
KR20040074004(A) |
申请公布日期 |
2004.08.21 |
申请号 |
KR20040009719 |
申请日期 |
2004.02.13 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
SCHLOESSER TILL;MANGER DIRK;GOEBEL BERND |
分类号 |
H01L21/8239;H01L21/8242;H01L27/105;H01L27/108;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/8239 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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