发明名称 |
COMPILER AND COMPILING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a compiler capable of creating a string of instructions by which processors capable of parallel processing can be operated with small power consumption. SOLUTION: Three instructions of a cycle of concern are rearranged to create six sequences of instructions (S61). For the slot of each of the instruction sequences, a humming distance between the bit patterns of operational codes between the instruction of concern and the instruction of the previous cycle is calculated (S64). This process is carried out for all the instructions of the three slots (S63-S65) and the sum of the humming distances is calculated (S66). The above processes are carried out for all of the six sequences of instructions (S62-S67). The sequence of instructions with which the sum of the six humming distances assumes a minimum value is selected and the instructions are switched around so that the sequence corresponding to the minimum value is provided (S68). The above processes are repeated from the second cycle to the final cycle (S60-S69). COPYRIGHT: (C)2004,JPO&NCIPI |
申请公布号 |
JP2004234126(A) |
申请公布日期 |
2004.08.19 |
申请号 |
JP20030019365 |
申请日期 |
2003.01.28 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
HEIJI TAKEHITO;OGAWA HAJIME;TANI TAKENOBU;SASAGAWA YUKIHIRO |
分类号 |
G06F9/302;G06F9/38;G06F9/45;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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