Technique for implementing chipkill in a memory system with X8 memory devices

摘要

A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in X4 and X8 memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. When operating in a X8 mode, all errors, including single-bit errors are corrected by the XOR memory engine. If more than one single bit error is detected on a single transaction, one or more of the errors may be corrected using ECC techniques.