发明名称 |
Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads |
摘要 |
The present invention provides a mechanism for handling interrupts on a processor that supports multiple-threads concurrently. The processor's resources are allocated to provide multiple logical processors. In response to a common interrupt, the logical processors vie for access to a shared register. The first logical processor to access the shared register handles the common interrupt. The remaining logical processors return from the interrupt. |
申请公布号 |
US6779065(B2) |
申请公布日期 |
2004.08.17 |
申请号 |
US20010945419 |
申请日期 |
2001.08.31 |
申请人 |
INTEL CORPORATION |
发明人 |
MURTY KESHAV;BOBHOLZ SCOTT |
分类号 |
G06F9/46;G06F;G06F9/00;G06F9/48;G06F13/24;(IPC1-7):G06F9/48 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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