发明名称 HETERO JUNCTION BIPOLAR TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To provide a hetero junction bipolar transistor with reduced offset voltage. SOLUTION: In the hetero junction bipolar transistor, an InGaP layer 10 is provided between a collector layer 4 and a base layer 5, so that a hetero barrier is formed between the collector layer 4 and the base layer 5 to reduce the offset voltage. Further, an In mixed crystal ratio of the InGaP layer 10 inserted into the collector layer 4 ranges within 0.52 to 0.60, whereby lattice matching of the InGaP layer 10 with the InGaAs base layer 5 is ensured. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004228137(A) 申请公布日期 2004.08.12
申请号 JP20030011155 申请日期 2003.01.20
申请人 HITACHI CABLE LTD 发明人 SATO SHIGEYOSHI
分类号 H01L21/331;H01L29/737;(IPC1-7):H01L21/331 主分类号 H01L21/331
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