| 摘要 |
PROBLEM TO BE SOLVED: To reduce the chip area by optimizing the arrangement of cells to minimize a channel region. SOLUTION: Compaction is executed for the chip in a way that the height of cells configuring a cell row, and a minimum interval between the adjacent cells is to be a maximum cell interval H1. Since the compaction is executed for the entire chip, and the wiring region is reduced, the chip area is decreased. Further, since the compaction is executed for the chip, the compaction keeping all the cell interval of the two cell rows the same, and thereafter the channel region is decreased, the compaction is executed for the entire chip, and the wiring region is reduced, then the chip area is reduced without a limit that the height of the chip cell rows is constant. COPYRIGHT: (C)2004,JPO&NCIPI
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