发明名称 LOGIC SYNTHESIZER AND LOGIC SYNTHESIS METHOD
摘要 PROBLEM TO BE SOLVED: To provide a logic synthesizer and a logic synthesis method which can easily perform determination whether insertion of a test point is proper or not, and can attempt to shorten design period by making the number of times of logic synthesis into one time. SOLUTION: This logic synthesizer is constituted using at least following parts; a logic gate circuit generating part 1 which generates a plurality of logic gate circuits of equivalent function based on behavioral description of a resistor transfer level; a test point insertion determination part 2 which determines whether insertion of a test point is necessary or not to each of the logic gate circuits, and inserts the test point when it is determined that insertion of the test point is necessary; an area calculating part 3 which calculates an area about each of the logic gate circuits for which processing by the test point insertion determination part is finished; and a logic synthesis part 4 which performs logic synthesis selecting the logic gate circuit having the smallest area. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004227517(A) 申请公布日期 2004.08.12
申请号 JP20030017899 申请日期 2003.01.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRANO YOKO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址