| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor test circuit for remarkably reducing an amount of a scanning test pattern and shortening a full scanning test time by modifying the constitution of an inside scanning chain at any time without increasing a test terminal and remarkably shortening a once-scanning shift action period in an LSI full scanning design, and to provide its test method. SOLUTION: The semiconductor test circuit for performing the LSI full scanning test by dividing a large number of the scanning chains comprises discrimination circuits 5 and 6 having an outside scanning-in terminal 9, an outside scanning-out terminal 10, a shift operation changeover terminal 11 and a clock terminal 12, and discriminating a specific cycle during shift operation changeover, and selection circuits 7 and 8 for selecting inside scanning-in and inside scanning-out connecting the outside scanning-in terminal 9 and the outside scanning-out terminal 10 on the basis of data for a command of a signal input from the outside scanning-in terminal 9 in the specific cycle. COPYRIGHT: (C)2004,JPO&NCIPI
|
