| 摘要 |
A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a block of cache lines from cache to memory. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that writes back data corresponding to each of the cache lines within the block.
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