METHOD OF IMPROVING EFFICIENCY OF WAFER ALIGNMENT USING DUMMY PATTERN OF SCRIBE LINE

摘要

PURPOSE: A method is provided to improve the efficiency of wafer alignment by inserting additionally a dummy pattern to a scribe line regardless of real design. CONSTITUTION: An interlayer dielectric(1) is formed on a semiconductor substrate with a predetermined structure and planarized by using CMP(Chemical Mechanical Polishing). A desired pattern is formed by adding a specific pattern(11) for failure inspection and review to a conventional via forming pattern. Then, the interlayer dielectric is selectively etched by using the desire pattern as an etching mask.