发明名称 |
Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices |
摘要 |
An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over. |
申请公布号 |
US2004153923(A1) |
申请公布日期 |
2004.08.05 |
申请号 |
US20030667199 |
申请日期 |
2003.09.18 |
申请人 |
STMICROELECTRONICS PVT, LTD. |
发明人 |
GOEL ASHISH KUMAR;KHANNA NAMERITA;AGGARWAL DAVINDER |
分类号 |
G01R31/28;G06F11/14;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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