| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory device capable of further improving a hit rate, and having a short mishit penalty time. SOLUTION: This cache memory device is equipped with: a coincidence detection circuit 113 for comparing a cache tag memory 111 with an address stored in an input address; a control circuit 110 for executing a data update process by transferring data from an external memory 130 in detecting inconsistency; an address storage circuit 116 for updating the input address in processing data update; an address update circuit 560 for updating the input address to output it to the detection circuit 113 in a pause of operation from the outside or during the data update process; and an update information storage circuit 573 for storing acceptability information of the data update process according to the results of the comparison of the update address with the address of the memory 111 by the detection circuit 113. When a next address succeeding a mishit address is mishit as well, the address is continuously updated, and when coincidence is detected by the detection circuit 113, the data update process for a memory 112 is continuously executed. COPYRIGHT: (C)2004,JPO&NCIPI
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