| 发明名称 |
Layout technique for address signal lines in decoders including stitched blocks |
| 摘要 |
A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.
|
| 申请公布号 |
US2004150735(A1) |
申请公布日期 |
2004.08.05 |
| 申请号 |
US20040760480 |
申请日期 |
2004.01.21 |
| 申请人 |
TSAI RICHARD H. |
发明人 |
TSAI RICHARD H. |
| 分类号 |
G11C7/00;G11C8/00;H01L27/146;H04N5/335;H04N5/376;(IPC1-7):H04N5/335 |
主分类号 |
G11C7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
