| 摘要 |
PURPOSE: An internal clock buffer strobing signal generation circuit is provided to improve operation speed by generating an internal clock without a standby time after enabling a clock at a power-down exit. CONSTITUTION: An internal clock buffer strobing signal generation circuit includes a first path for receiving an external clock as an internal clock and a second path for generating the internal clock. The second path includes a first input unit for inputting a first signal having precharge states of two banks, a second input unit for inputting a second signal as clock enable signal for power-down exit faster than an internal clock enable signal, and a logical combination part for detecting active states of the first and the second input units.
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