发明名称 |
High speed tester with narrow output pulses |
摘要 |
A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.
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申请公布号 |
US6771061(B2) |
申请公布日期 |
2004.08.03 |
申请号 |
US20020245534 |
申请日期 |
2002.09.17 |
申请人 |
TERADYNE, INC. |
发明人 |
SARTSCHEV RONALD A.;XU JUN |
分类号 |
G01R31/319;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/319 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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