VERTICAL TYPE INSULATED GATE FIELD EFFECT TRANSISTOR

摘要

PROBLEM TO BE SOLVED: To provide a vertical type insulated gate field effect transistor reduced in the number of manufacturing process compared with that of a conventional field effect transistor, without increasing the rate of an area occupied by the chip of a bidirectional Zener diode formed in the same chip by the shape of a diffusion layer as the protective diode of a power MOSFET. SOLUTION: The vertical type insulated gate field effect transistor is provided with a P-base region 25 and, at the same time, a P-type diffusion layer 23 having a pattern area smaller than the P-base region 25, which are formed in an N--drain region 21, and an N+-type source region 26 and, at the same time, N+-type diffusion layer 24, which are formed in the P-type diffusion layer 23, while the bidirectional Zener diode ZDGconnected between the drain gates is constituted of the N--drain region 21, the P-type diffusion layer 23, and the N+-type diffusion layer 24. COPYRIGHT: (C)2004,JPO&NCIPI