| 摘要 |
A memory architecture design and strategy of the present invention uses memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral controller services, overall performance in this mode is optimized. The surprising result is that even though the choice of memory is inappropriate for the task based on the precepts of the prior art, the overall memory system is effective. One example of a normally disadvantageous situation that is beneficial in connection with one or more embodiments of the present invention is bank switching in DDR-SDRAM, thereby achieving feasibility without resort to, for example, SRAM.
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