发明名称 Nonvolatile semiconductor memory
摘要 A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT-EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
申请公布号 US2004141378(A1) 申请公布日期 2004.07.22
申请号 US20040756267 申请日期 2004.01.14
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TANZAWA TORU;TAURA TADAYUKI;KURIYAMA MASAO
分类号 G11C16/00;G11C16/30;G11C16/34;(IPC1-7):G11C11/34 主分类号 G11C16/00
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