发明名称 Net segment analyzer for chip CAD layout
摘要 A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.
申请公布号 US2004143809(A1) 申请公布日期 2004.07.22
申请号 US20030349564 申请日期 2003.01.22
申请人 COWAN JOSEPH W.;BLACKWOOD JEFFREY E.;MYERS TRACY D. 发明人 COWAN JOSEPH W.;BLACKWOOD JEFFREY E.;MYERS TRACY D.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
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