| 摘要 |
System and method for implementing a clock gater circuit are described. One embodiment is a clock gater circuit comprising an output clock signal generator electrically connected between a clock input for receiving an input clock signal and a clock output; a switch for selectively enabling or disabling generation of a clock signal by the output clock signal generator; and circuitry for causing a voltage level of the clock signal generated by the output clock signal generator to maintain a current voltage thereof responsive to a qualifier signal voltage level.
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