发明名称 Method for improving process step sequence in forming semiconductor memories with charge trapping memory cells, used same masks as used for forming doped troughs outside memory cell field for removing HV gate dielectric
摘要 In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.
申请公布号 DE10259783(A1) 申请公布日期 2004.07.15
申请号 DE20021059783 申请日期 2002.12.19
申请人 INFINEON TECHNOLOGIES AG 发明人 PARASCANDOLA, STEFANO;HABERKERN, ROLAND;CASPARY, DIRK;KNOEFLER, ROMAN;HAUFE, JUERG;KLEINT, CHRISTOPH;SCHULZE, NORBERT;POLEI, VERONIKA;SACHSE, JENS-UWE;DEPPE, JOACHIM;RIEDEL, STEPHAN;LUDWIG, CHRISTOPH;HAIBACH, PATRICK;STEIN VON KAMIENSKI, ELARD
分类号 H01L21/8246;H01L27/115;(IPC1-7):H01L21/824;H01L21/824 主分类号 H01L21/8246
代理机构 代理人
主权项
地址