| 摘要 |
PROBLEM TO BE SOLVED: To provide a semocoductor memory device which operates stably at a high speed by suppressing the lowering of power voltage without increasing a circuit scale. SOLUTION: In the memory device, array power generating circuits each of which supplies an array power voltage Vdds to a corresponding array block and peripheral power generating circuits each of which supplies a peripheral power voltage Vddp to a peripheral circuit are provided at surroundings of respective memory array blocks. Respective power voltages are formed under the same reference voltage and are transmitted to array power lines APLs or peripheral power lines CPLs. N-channel MOS transistors Tr5, Tr6 are connected among the array power lines APLs of array power generating circuits 1a, 2a and the peripheral power line CPL of a peripheral power generating circuit 5b. When the transistors Tr5, Tr6 are turned on by receiving boosted voltages Vpp at the gates, the lines APLs is coupled with the line CPL electrically. COPYRIGHT: (C)2004,JPO&NCIPI
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