发明名称 |
Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description |
摘要 |
A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.
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申请公布号 |
US6763489(B2) |
申请公布日期 |
2004.07.13 |
申请号 |
US20010773541 |
申请日期 |
2001.02.02 |
申请人 |
LOGICVISION, INC. |
发明人 |
NADEAU-DOSTIE BENOIT;COTE JEAN-FRANCOIS |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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