发明名称 |
Super-coherent multiprocessor system bus protocols |
摘要 |
A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.
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申请公布号 |
US6763435(B2) |
申请公布日期 |
2004.07.13 |
申请号 |
US20010978355 |
申请日期 |
2001.10.16 |
申请人 |
INTERNATIONAL BUISNESS MACHINES CORPORATION |
发明人 |
ARIMILLI RAVI KUMAR;GUTHRIE GUY LYNN;STARKE WILLIAM J.;WILLIAMS DEREK EDWARD |
分类号 |
G06F12/08;G06F13/00;G06F13/14;(IPC1-7):G06F13/14 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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