发明名称 |
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing |
摘要 |
A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
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申请公布号 |
US2004132271(A1) |
申请公布日期 |
2004.07.08 |
申请号 |
US20030338156 |
申请日期 |
2003.01.08 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
ANG CHEW HOE;LIM ENG-HUA;LIANG CHA RANDALL CHER;ZHENG JIA ZHEN;QUEK ELGIN;ZHOU MEI-SHENG;YEN DANIEL |
分类号 |
H01L21/268;H01L21/28;H01L21/8238;H01L29/49;(IPC1-7):H01L21/823;H01L21/320;H01L21/476 |
主分类号 |
H01L21/268 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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