Integrated memory circuit with several memory cells, has self-testing unit and redundancy analysis memory and computer unit to detect defective memory cells so that they can be replaced by redundant cells

摘要

Method for testing an integrated circuit memory having a main memory (SP) with several data storage units, whereby test data is applied to a data storage unit and the output test data read from the main memory and compared in a self test unit (STE) with expected output test data. Any data differences are stored in a redundancy analysis memory (RAS) prior to analysis by a computer unit (RE). Based on the results of the analysis a repair strategy is determined involving redundant rows and/or columns. An Independent claim is made for an integrated memory with means for detection and correction of errors.