发明名称 Power voltage supply distribution architecture for a plurality of memory modules
摘要 The invention relates to an architecture for distributing supply voltages to a plurality of memory modules (Mod1, ..., ModN) supplied through a plurality of charge pump circuits (Pump1, ..., PumpM). <??>Advantageously according to the invention, the architecture for distributing supply voltages comprises a sorting block (11) bidirectionally-connected to the plurality of memory modules (Mod1, ..., ModN) from which it receives a plurality of power requests and it is capable of providing a sorting signal (ORD) of said power requests on the basis of a priority scale in order to drive the plurality of charge pump circuits (Pump1, , PumpM) and distribute convenient supply voltages (Vhigh1, ..., VhighN; Vneg1, ..., VnegN) to the plurality of memory modules (Mod1, ..., ModN). Moreover, this architecture is software-configurable. <IMAGE>
申请公布号 EP1435621(A1) 申请公布日期 2004.07.07
申请号 EP20020425809 申请日期 2002.12.30
申请人 STMICROELECTRONICS S.R.L. 发明人 PASOTTI, MARCO;DE SANDRE, GUIDO;IEZZI, DAVID;MUZZI, GILBERTO;POLES, MARCO
分类号 G06F1/26;G11C5/14;G11C16/30;(IPC1-7):G11C5/14;H02M3/07 主分类号 G06F1/26
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