| 摘要 |
PURPOSE: A method for manufacturing a transistor provided to minimize short channel effect and to reduce reverse short channel effect by local channel implanting using a dummy gate pattern. CONSTITUTION: A stacked pad pattern including the first oxide layer, the first nitride layer, the second oxide layer and the second nitride layer is formed on a silicon substrate(1). A trench is formed at an STI region of the substrate. The first insulating layer(8) is formed on the resultant structure. By removing the stacked pad pattern, a dummy gate pattern is formed. An LDD region is formed in the substrate. The third nitride spacer is formed at both sidewalls of the dummy gate pattern. A source(12a) and a drain(12b) are formed in the substrate. The fourth nitride layer(13) is formed on the resultant structure. By performing local channel implanting, a local channel region is formed on the substrate of the gate region. The third insulating layer(17) is formed on the resultant structure. A gate electrode(18) is formed in the gate region. The fourth insulating layer(19) is formed. Then, a gate plug(20a), a source plug(20b) and a drain plug(20c) are formed.
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