| 摘要 |
A multiplexer for use with switching apparatus for data communication networks. The multiplexer topology includes two or more groupings, or sections, each containing a plurality of individual channels. Each of the channels has an input buffer amplifier and an output Ft-doubler circuit. The outputs of all of the channels within a each particular channel section are connected in parallel relation, and fed to respective common-base transistor amplifiers. The outputs of all of the common-base amplifiers for each channel section, in turn, are connected in parallel and fed to the inputs of a pair of emitter-follower amplifiers. Through the use of selectively actuated current sources, each multiplexer channel is normally biased off, unless that channel is selected for a switching operation. Bleeder current sources are applied to the emitters of the common-base amplifiers to reduce output jitter from the channels which are biased off. The multiplexer architecture provides high speed operation from channel sectioning, and low power consumption by reducing both the amount of current drawn and the voltage potential necessary, to operate the multiplexer.
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