发明名称 METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming a metal line of a semiconductor device is provided to enhance the reliability by preventing deterioration of a sidewall of a via hole and improving an adhesive characteristic of an interlayer dielectric. CONSTITUTION: A dual damascene pattern including a via hole and a trench is formed on an interlayer dielectric(102,106) of a semiconductor substrate(101) in order to expose a predetermined region of a lower metal line(105) through the via hole. A silicide layer(109) is formed on the exposed region of the lower metal line by performing a silicide process. The silicide layer is removed from the lower metal line. The silicide layer is redeposited on a sidewall of the via hole by performing a sputtering etch process. The dual damascene pattern is buried by a conductive material in order to form an upper metal line(112) and a via plug.
申请公布号 KR20040058951(A) 申请公布日期 2004.07.05
申请号 KR20020085471 申请日期 2002.12.27
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, DONG JUN
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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