发明名称 RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED RESISTOR SET
摘要 PROBLEM TO BE SOLVED: To operate a large-scale context switch by using a minimum quantity of overheads. SOLUTION: An RISC (Reduced Instruction Set Computer) microprocessor architecture is provided with banks, each has a plurality of same-type resistor sets, for a data processor operated in a plurality of modes. A data processor controls access to eliminate the need for specifying any of the given banks through a command and a process. An integer register set includes a first subset, a second subset, and a shadow subset. The command accesses the first and the second sub-sets while the data processor is in a first mode. The command accesses the first subset while the data processor is in a second mode. However, when the command attempts to access the second subset, the command is directed to the shadow sub-set. A user routine saves data written on the second sub-set to seemingly use the second sub-set without reconstitution. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004185637(A) 申请公布日期 2004.07.02
申请号 JP20040010368 申请日期 2004.01.19
申请人 TRANSMETA CORP 发明人 GARG SANJIV;LENTZ DEREK J;NGUYEN LE TRONG;CHEN SHO LONG
分类号 G06F9/30;G06F9/305;G06F9/318;G06F9/34;G06F9/38;G06F9/42;G06F9/46;G06F9/48;(IPC1-7):G06F9/46 主分类号 G06F9/30
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