| 摘要 |
Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.
|
