METHOD FOR PLANARIZING INTERLAYER DIELECTRIC OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for planarizing an interlayer dielectric of a semiconductor device is provided to improve process yield by omitting a CMP(chemical mechanical polishing) process in planarizing an interlayer dielectric and by excluding a process condition occurring in a polishing process. CONSTITUTION: A metal layer is deposited on a lower thin film(10) and is patterned to form a metal interconnection pattern(20). An oxide layer(30) is thinly deposited on the lower thin film having the metal interconnection pattern. An HDP(high density plasma) insulation layer(60) is formed on the lower thin film having the deposited oxide layer. The first SOG(spin on glass) insulation layer(70) is deposited on the lower thin film having the deposited HDP insulation layer. A TEOS(tetraethoxysilane) insulation layer(80) is deposited on the lower thin film having the deposited first SOG insulation layer.