发明名称 Priority resolver and near match detection circuit
摘要 An apparatus and method is disclosed for a CAM priority match detection circuit which determines a "near match" condition using a current-based decoder. The decoder uses n input lines and m complement lines to generate 2<n >outputs, where the 2n outputs form a priority code for a given CAM word. The priority match detection circuit determines which CAM word or words out of a plurality of CAM words has the least amount of mismatching bits and prioritizes the CAM word or words in accordance with such determination.
申请公布号 US2004128436(A1) 申请公布日期 2004.07.01
申请号 US20020330208 申请日期 2002.12.30
申请人 REGEV ALON;REGEV ZVI 发明人 REGEV ALON;REGEV ZVI
分类号 G11C15/00;(IPC1-7):G06F12/00 主分类号 G11C15/00
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