发明名称 Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands
摘要 In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.
申请公布号 US2004128573(A1) 申请公布日期 2004.07.01
申请号 US20020334115 申请日期 2002.12.31
申请人 SPERBER ZEEV;ANATI ITTAI;BUSTAN YUVAL;LAHAV SAGI 发明人 SPERBER ZEEV;ANATI ITTAI;BUSTAN YUVAL;LAHAV SAGI
分类号 G06F1/32;G06F9/302;(IPC1-7):G06F1/32 主分类号 G06F1/32
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