| 发明名称 |
Self-aligned planar double-gate process by amorphization |
| 摘要 |
The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.
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| 申请公布号 |
US2004121549(A1) |
申请公布日期 |
2004.06.24 |
| 申请号 |
US20020328234 |
申请日期 |
2002.12.23 |
| 申请人 |
DOKUMACI OMER H.;DORIS BRUCE B.;HEGDE SURYANARAYAN G.;IEONG MEIKEI;JONES ERIN C. |
发明人 |
DOKUMACI OMER H.;DORIS BRUCE B.;HEGDE SURYANARAYAN G.;IEONG MEIKEI;JONES ERIN C. |
| 分类号 |
H01L21/265;H01L21/336;H01L21/337;H01L29/423;H01L29/49;H01L29/786;H01L29/80;(IPC1-7):H01L21/337 |
主分类号 |
H01L21/265 |
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