| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a digital matched filter for reducing a computing amount and power consumption by storing a value once calculated in a storage means and reusing the value. <P>SOLUTION: Three-stages of shift registers 21 receive a reception signal Rx(i) after A/D conversion in a W-CDMA receiver, adders 22, 23 sum outputs of each stage, an adder 24 sums the result of sums to calculate a code C configuring a partial code string a, a subtractor 25 subtracts the result of the sums to calculate a code D configuring the partial code string a, shift registers 26, 27 receive the codes C, D, respectively, and an arithmetic circuit 28 applies prescribed arithmetic processing to the output of a prescribed stage of the shift registers 26, 27 to apply correlation arithmetic operations to the partial code sequence (a). The correlation arithmetic results are sequentially stored in prescribed addresses of a random access memory 31, arithmetic circuits 32, 33 read the stored data and process the data to apply correlation arithmetic operations to division codes A, B and a filter output is obtained on the basis of the arithmetic results. <P>COPYRIGHT: (C)2004,JPO</p> |
