发明名称 READOUT CONTROL CIRCUIT AND FIFO CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a readout control circuit and a FIFO(First-in First-out) control circuit which can shorten a period of time from the start of write-in to the start of reading. SOLUTION: The readout control circuit 22a is provided with an enable signal generating circuit 21a which generates an enable signal ES by detecting the start of write-in based on a write-in clock CLK<SB>1</SB>at the time of write-in operation and a reset signal generating circuit 6 which outputs a reset signal RS to the enable signal generating circuit 21a by detecting the completion of write-in. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004178671(A) 申请公布日期 2004.06.24
申请号 JP20020342591 申请日期 2002.11.26
申请人 TOSHIBA CORP 发明人 HASEGAWA SHINYA
分类号 G06F13/38;G11C7/00;(IPC1-7):G11C7/00 主分类号 G06F13/38
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