| 摘要 |
<P>PROBLEM TO BE SOLVED: To correctly and stably generate a plurality of internal clock signals with different phases and/or frequencies. <P>SOLUTION: An operation control signal (Iref) for an oscillator (3) for generating an internal clock signal (CLK1) subjected to phase synchronization with the phase of a basic clock signal (BCLK) is given to a second internal clock generation circuit (10). In the second internal clock generation circuit, a control signal for adjusting a phase/frequency difference between a synchronous object signal (DATA) and a second internal clock signal is generated with the given operation control signal as a reference to adjust the phase/frequency of the second internal clock signal. <P>COPYRIGHT: (C)2004,JPO |
