发明名称 |
Reduced latency wide-I/O burst architecture |
摘要 |
A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls. For every I/O, eight bits of data are presented to a 9-to-1 multiplexer. The first of eight bits in the burst sequence is the access time-limiting bit and is preselected by the burst base addresses of the 9-to-1 multiplexer. Subsequent bits in the burst sequence have extra half-cycles to be output, and use look-aside 8-to-1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings.
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申请公布号 |
US6754135(B2) |
申请公布日期 |
2004.06.22 |
申请号 |
US20020065056 |
申请日期 |
2002.09.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PILO HAROLD |
分类号 |
G06F13/00;G11C7/00;G11C7/10;(IPC1-7):G11C7/00 |
主分类号 |
G06F13/00 |
代理机构 |
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