| 摘要 |
A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating. |
